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专利名称：Circuit for generating phase comparison
signal
发明人：In-Chul Jung申请号：US10746519申请日：20031224公开号：US07057428B2公开日：20060606
专利附图：
摘要：A delay locked loop (DLL) circuit in a synchronous dynamic random accessmemory includes a phase comparison signal generating circuit for generating a phasecomparison reference signal by receiving a clock signal, wherein the phase comparison
reference signal maintaining a first logic level longer than one period of a clock signalthrough a clock dividing operation, a delay chain for delaying an inverted phase
comparison reference signal in response to a delay chain adjusting signal, a delay modelfor compensating a delay of a internal circuit by receiving an output signal of the delaychain and a phase comparator for comparing phase of the phase comparison referencesignal and an output signal of the delay model.
申请人：In-Chul Jung
地址：Ichon-shi KR
国籍：KR
代理机构：Blakely Sokoloff Taylor & Zafman
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