MEMORY存储芯片MT48LC8M32LFB5-8IT中文规格书

When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQoutputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 withall other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for thelower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQSand UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on ax16 enable each byte lane to be leveled independently.

The write leveling mode register interacts with other mode registers to correctly config-ure the write leveling functionality. Besides using MR1[7] to disable/enable write level-ing, MR1[12] must be used to enable/disable the output buffers. The ODT value, burstlength, and so forth need to be selected as well. This interaction is shown in Table 71. Itshould also be noted that when the outputs are enabled during write leveling mode, theDQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during writeleveling mode, only the DQS strobe terminations are activated and deactivated via theODT ball. The DQ remain disabled and are not affected by the ODT ball.

Table 71: Write Leveling Matrix

Note 1 applies to the entire tableMR1[7]WriteLevelingDisabledEnabled(1)Disabled(1)MR1[12]OutputBuffersMR1[2, 6, 9]RTT,nomValuen/aDRAMRTT,nomDRAMODT BallDQSLowOffDQOffDRAM StateWrite leveling not enabledDQS not receiving: not terminatedPrime DQ High-Z: not terminatedOther DQ High-Z: not terminatedDQS not receiving: terminated by RTTPrime DQ High-Z: not terminatedOther DQ High-Z: not terminatedDQS receiving: not terminatedPrime DQ driving CK state: not terminatedOther DQ driving LOW: not terminatedDQS receiving: terminated by RTTPrime DQ driving CK state: not terminatedOther DQ driving LOW: not terminatedCaseNotes012See normal operationsΩΩΩΩ, or120ΩEnabled(0)n/aHighOn2LowOff33ΩΩ, or120ΩNotes:

HighOn41.Expected usage if used during write leveling: Case 1 may be used when DRAM are on a

dual-rank module and on the rank not being leveled or on any rank of a module notbeing leveled on a multislot system. Case 2 may be used when DRAM are on any rank ofa module not being leveled on a multislot system. Case 3 is generally not used. Case 4 isgenerally used when DRAM are on the rank that is being leveled.

2.Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,

and all RTT,nom values are allowed. This simulates a normal standby state to DQS.

3.Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, andonly some RTT,nom values are allowed. This simulates a normal write state to DQS.

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Mode Register 2 (MR2)

Figure 53: READ Latency (AL = 5, CL = 6)

BC4

CK#CKCommandACTIVE nREAD ntRCD (MIN)T0T1T2T6T11T12T13T14NOPNOPNOPNOPNOPNOPDQS, DQS#AL = 5DQRL = AL + CL = 11CL = 6DOnDOn + 1DOn + 2DOn + 3PDF: 09005aef8591dc1f

8Gb_DDR3L.pdf - Rev. C 10/15 EN

8Gb: x4, x8, x16 DDR3L SDRAMMode Register 2 (MR2)Figure 54: Mode Register 2 (MR2) DefinitionBA2BA1BA0A13A12A11A10A9A8A7A6A5A4A3A2A1A0Address bus161514131211109876R11111TT(WR)0SRTASR010000543CWL210100101Mode register 2 (MR2)M15M1400110101Mode Register Mode register set 0 (MR0)Mode register set 1 (MR1)Mode register set 2 (MR2)Mode register set 3 (MR3)M7 Self Refresh Temperature01Normal (0°C to 85°C)Extended (0°C to 95°C)M5M4M30000110011001101010101 CAS Write Latency (CWL)5 CK (tCK ≥2.5ns)6 CK (2.5ns tCK ≥1.875ns)7 CK (1.875ns tCK ≥1.5ns)8 CK (1.5ns tCK ≥1.25ns)9 CK (1.25ns tCK ≥1.07ns)10 CK (1.07ns tCK ≥0.938ns)ReservedReservedM10M900110101Dynamic ODT(RTT(WR))RTT(WR) disabledRZQ/4RZQ/2ReservedM6Auto Self Refresh0Disabled: Manual 1Enabled: Automatic11Note:1.MR2[18, 15:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.

CAS WRITE Latency (CWL)

CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of theinternal write to the latching of the first data in. CWL must be correctly set to the corre-sponding operating clock frequency (see Figure 54 (page 136)). The overall WRITE la-tency (WL) is equal to CWL + AL (Figure 52 (page 132)).

Figure 55: CAS WRITE Latency

CK#CKCommandT0T1T2T6T11T12T13T14ACTIVE nWRITE ntRCD (MIN)NOPNOPNOPNOPNOPNOPDQS, DQS#AL = 5DQWL = AL + CWL = 11CWL = 6DI nDI n + 1DI n + 2DI n + 3Indicates breakin time scale

Transitioning DataDon’t Care

AUTO SELF REFRESH (ASR)

Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en-PDF: 09005aef8591dc1f

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Mode Register 3 (MR3)

and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commandsare redirected to the multipurpose register. The resulting operation when either a READor a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (seeTable 74 (page 140)). When the MPR is enabled, only READ or RDAP commands are al-lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).Power-down mode, self refresh, and any other nonREAD/RDAP commands are not al-lowed during MPR enable mode. The RESET function is supported during MPR enablemode.

Figure 57: Multipurpose Register (MPR) Block Diagram

Memory coreMR3[2] = 0 (MPR off)Multipurpose registerpredefined data for READsMR3[2] = 1 (MPR on)DQ, DM, DQS, DQS#Notes:

1.A predefined data pattern can be read out of the MPR with an external READ com-mand.

2.MR3[2] defines whether the data flow comes from the memory core or the MPR. When

the data flow is defined, the MPR contents can be read out continuously with a regularREAD or RDAP command.

Table 73: MPR Functional Description of MR3 Bits

MR3[2]MPR0MR3[1:0]MPR READ Function“Don’t Care”FunctionNormal operation, no MPR transactionAll subsequent READs come from the DRAM memory arrayAll subsequent WRITEs go to the DRAM memory arrayEnable MPR mode, subsequent READ/RDAP commands defined by bits 1 and21A[1:0](see Table 74 (page 140))MPR Functional Description

The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remainingDQs driven LOW, or for all DQs to output the MPR data . The MPR readout supportsfixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READlatencies and AC timings applicable, provided the DLL is locked as required.

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ZQ CALIBRATION Operation

ZQ CALIBRATION Operation

The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON)and ODT values (RTT) over process, voltage, and temperature, provided a dedicated240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to VSSQ.

DDR3 SDRAM require a longer time to calibrate RON and ODT at power-up initializationand self refresh exit, and a relatively shorter time to perform periodic calibrations.

DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An exampleof ZQ calibration timing is shown below.

All banks must be precharged and tRP must be met before ZQCL or ZQCS commandscan be issued to the DRAM. No other activities (other than issuing another ZQCL orZQCS command) can be performed on the DRAM channel by the controller for the du-ration of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately cali-brate RON and ODT. After DRAM calibration is achieved, the DRAM should disable theZQ ball’s current consumption path to reduce power.

ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time.Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired.

In dual-rank systems that share the ZQ resistor between devices, the controller must notenable overlap of tZQinit, tZQoper, or tZQCS between ranks.

Figure 62: ZQ CALIBRATION Timing (ZQCL and ZQCS)

T0

T1

Ta0

Ta1

Ta2

Ta3

Tb0

Tb1

Tc0

Tc1

Tc2

CK#CK

CommandAddress

A10CKEODTDQ

ZQCLNOPNOPNOPValidValidValidValidValidValidValidValidActivitiesZQCSNOPNOPNOPValidValidValid123High-ZtZQinit or tZQoperValidValid123High-ZtZQCSValidValidActiv-itiesIndicates breakin time scale

Don’t Care

Notes:

1.CKE must be continuously registered HIGH during the calibration procedure.

2.ODT must be disabled via the ODT signal or the MRS during the calibration procedure.3.All devices connected to the DQ bus should be High-Z during calibration.

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