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专利名称：Methods of forming a transistor gate发明人：Chambers, James J.申请号：EP03104979.4申请日：20031224公开号：EP14359A2公开日：20040707
专利附图：
摘要：Methods are disclosed for fabricating transistor gate structures in which high-kdielectric layer roughness is reduced by formation of a nucleation promotion layer (120)over the substrate (104) or any intentional interface layers, and a high-k gate dielectric(130) is formed over the nucleation promotion layer (120). The nucleation promotion
layer has a thickness of 10 Å or less, such as a monolayer or a sub-monolayer, comprisinga metal, a metal silicide, or a metal silicate, which promotes uniform chemical vapordeposition of high-k gate dielectric materials by increasing the density of nucleation siteson the substrate or intentional interface layer.
申请人：Texas Instruments Inc.
地址：P.O. Box 655474 13500 North Central Expressway Dallas, Texas 75265 US
国籍：US
代理机构：Holt, Michael
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